This application claims the priority benefit of Taiwan application Ser. no. 90126668, filed on Oct. 29, 2001.
1. Field of Invention
The present invention relates to a structure of a non-volatile memory. More particularly, the present invention relates to a structure of a silicon nitride read-only memory (NROM).
2. Description of Related Art
Flash memory is an electrically erasable programmable read-only memory (EEPROM) that is widely used in computer and microprocessor systems for permanently storing information that are repeatedly read, written or erased. Moreover, flash memory can retain information even when power is interrupted.
A typical flash memory device is formed with a doped polysilicon floating gate and a control gate. The programming of a flash memory device is accomplished by applying an appropriate voltage to the source region, the drain region and the control gate and causing electrons to travel from the source region through the channel to the drain region. A portion of the electrons would pass through the tunnel oxide barrier under the polysilicon floating gate to enter the floating gate. The electrons that pass into the floating gate are evenly distributed in the polysilicon floating gate layer. This phenomenon of electron passing through the tunnel oxide barrier into the polysilicon floating gate layer is known as the tunneling effect. In general, the erasure of a flash memory is achieved by means of Fowler-Nordheim tunneling. The mechanism for programming a flash memory, on the other hand, is usually accomplished by channel hot-electron injection. However, when defects were present in the tunnel oxide layer under the polysilicon floating gate layer, current leakage would easily occur to adversely affect the reliability of the device.
To resolve the current leakage problem in a flash memory device, a charge-trapping layer is conventionally used to replace the polysilicon floating gate. Typically, an EEPROM is formed with a stacked gate structure that comprises a silicon oxide/silicon nitride/silicon oxide (ONO) structure, and the silicon nitride layer of the ONO structure serves as the charge-trapping layer. Because the silicon nitride charge-trapping layer functions as the floating gate of the read-only memory, this type of EEPROM is also known as silicon nitride read-only memory (NROM). Since the silicon nitride layer tends to trap charges, the electrons that are injected into the silicon nitride are not evenly distributed in the entire silicon nitride. Instead, the electrons are distributed in a Gaussian manner in the silicon nitride. Since the electrons injected into the silicon nitride are concentrated in a localized region, the presence of defect in the tunnel oxide layer is not as magnified. The current leakage problem in the device is thus mitigated.
Another advantage of having a silicon nitride layer to serve as the floating gate is because electrons are stored locally in the channel near the top of either the source region or the drain region. In other words, a NROM has the advantage for storing 2 bits of memory in a single cell. The programming of a NORM can accomplish by first applying voltages to the source region at the end of the stacked gate and to the control gate, and trapping electrons at the end of the stacked gate near the source region. Voltages can further be applied to the drain region at the other end of the stacked gate and to the control gate, and trapping electrons at the end of the stacked gate near the drain region. By applying voltages to the control gate and to the source region or drain region at the side of the stacked gate, two groups of electrons, a single group of electrons or no electron can be stored in the silicon nitride. Using silicon nitride as the floating gate for a flash memory device can thereby provide four types of configuration in a single memory cell and form a 2-bit memory in one cell type of flash memory device.
During the fabrication of a silicon nitride read-only memory, plasma is often used in the process. Charges that are generated in the plasma process would move along the metal interconnects. Such a phenomenon is known as the xe2x80x9cantenna effectxe2x80x9d. When a transient charge unbalance occurs, a portion of the charges is injected into the ONO layer to induce a programming effect. A large threshold voltage variation, 0.3 volts to 0.9 volts, is thereby resulted.
A conventional approach to resolve the programming effect in a silicon nitride read-only memory resulted from the xe2x80x9cantenna effectxe2x80x9d is to form a diode in the substrate to electrically connect with the word line. When the transient charges reach a specific value, the device is discharged by an electrical breakdown of the diode. However, when the voltage induced by the charges is less than the breakdown voltage of the diode, the charges are still injected into the ONO layer to induce the programming effect. Moreover, such a design will lower the input voltage and decreases the speed of the writing operation.
The present invention provides a silicon nitride read-only memory that prevents the antenna effect in which the charges generated during the manufacturing process are conducted to the substrate to prevent the ONO composite layer of the non-volatile read-only memory from being damaged or programmed. The input voltage is not lowered to adversely affect the operating speed of the device when the memory device is being used.
The present invention provides a silicon nitride read-only memory that prevents the antenna effect. This read-only memory comprises a word line, an electron-trapping layer and a metal protection line. The word line covers the substrate, wherein the word line comprises a silicide layer and a polysilicon layer. The electron-trapping layer is located between the word line and the substrate. The electron-trapping layer is the silicon nitride layer of a silicon oxide/silicon nitride/silicon oxide composite structure layer. The metal protection line covers the substrate, connecting the word line and a grounding doped region in the substrate, wherein the resistance of the metal protection line is higher than that of the word line.
According to the present invention, a metal protection line is formed to conduct the charges generated during the plasma-containing manufacturing process to the grounding doped region in the substrate through the metal protection line and the contact. The transient unbalance charges are thus conducted to the substrate to prevent the trapping of charges in the silicon oxide/silicon nitride/silicon oxide composite layer.
Moreover, the resistance of the metal protection line is higher than that of the word line, a high current can be used to burn out the metal protection line after the manufacturing process is completed (fab-out). During the operation of the silicon nitride read-only memory device with a metal protection line, the operational voltage is not lower to slow the operating speed.
Accordingly, the charges generated during the fabrication process are conducted to the substrate to protect the silicon oxide/silicon nitride/silicon oxide composite layer of the non-volatile read-only memory from being damaged or falsely programmed. Furthermore, a high current can be used to burn out the metal protection line after the manufacturing process is completed, allowing the read-only memory to operate normally.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide farther explanation of the invention as claimed.